Today's electronic components are designed so that they will function properly when used with components from a variety of manufacturers. For example, memory devices, such as dynamic random access memory (“DRAM”) devices, are designed to function properly with memory controllers and other components available from a variety of sources.
To ensure performance and allow component compatibility, the operating characteristics and parameters of electronic devices are specified in substantial detail. Other electronic devices are then designed to properly interface with the electronic device based on the specification. For example, specifications for Synchronous Dynamic Random Access Memory (SDRAM) devices generally specify a range of supply voltages that can be used to power the SDRAM devices. The specification also identifies the acceptable ranges of the rise- and fall-time slew rates (Volts/nanosecond) of read data signals output from the SDRAM devices. To meet the specification, an SDRAM device must be capable of meeting each parameter at any value of each of the other specified parameters. Therefore, SDRAM devices must be capable of outputting read data signals having the specified rise- and fall-time slew rates throughout the range of specified supply voltages. It can also be important that the slew rates of the read data signals not vary as operating parameters, such as the supply voltage, are varied. Unfortunately, both the rise-time and fall-time slew rates of read data signals output from conventional SDRAM devices often vary significantly with supply voltage variations. These variation can make it difficult to meet the slew rate specifications at all supply voltages within the specified range.
As the operating speed of SDRAM devices and associated devices continues to increase, the variations in slew rate as a function of supply voltage variations can become a more significant problem. Problems resulting from slew rate variations have also become more significant in double-data rate (DDR) SDRAM devices, which output read data on both the rising edge and the falling edge of a read data strobe that is synchronized to a master clock signal.
FIG. 1 shows a conventional output buffer 10 commonly in use in DDR SDRAMs. The output buffer 10 includes a first pre-driver 14 containing a first inverter 16 that receives an active high D_PUP signal, and a second inverter 18 that receives an active low D_PDN_signal. As explained below, the D_PUP signal is activated high to output a high read data output signal, and the D_PDN_signal is activated low to output a low read data output signal.
The inverter 16 generates an active low PUPEN_signal from the D_PDN_signal, and the inverter 18 generates an active low PDNEN_signal from the D_PDN_signal. These signals are applied to a second pre-driver 20. The PUPEN_signal is applied to one input of a NOR gate 22 having an output that drives an inverter 24, which, in turn, outputs an active low PUP_signal. A second input of the NOR gate 22 receives a DQEN_signal, which is active low when read data are to be output from the output buffer 10. Thus, the PUP_signal is active low to cause the output buffer 10 to output a high read data signal whenever the NOR gate 22 is enabled by a low DQEN_signal and the D_PUP signal is active high. Similarly, the PUPEN signal is applied to one input of a NAND gate 26 having an output that drives an inverter 28, which, in turn, outputs an active high PDN signal. A second input of the NAND gate 26 receives a DQEN signal, which the compliment of the DQEN_signal. The DQEN signal is active high when read data are to be output from the output buffer 10. Thus, the PDN signal is active high to cause the output buffer 10 to output a low read data signal whenever the NAND gate 26 is enabled by a high DQEN signal and the D_PDN signal is active high.
The output buffer 10 includes a final driver 30 having a PMOS transistor 32 coupled between a positive supply voltage VCCQ and a data output terminal DQ_OUT through a resistor 34. The output buffer 10 also includes an NMOS transistor 36 coupled between a negative supply voltage VSSQ, which will assumed to be ground, and the data output terminal DQ_OUT through a resistor 38. The data output terminal DQ_OUT is biased to a suitable voltage, which is typically VCCQ/2, through a resistor 40.
The DQ_OUT terminal is normally at VCCQ/2 when the PUP_signal is inactive high and the PDN signal is inactive low. When the PUP_signal is active low and the PDN signal is inactive low, the PMOS transistor 32 turns ON to couple the DQ_OUT terminal to VCCQ. When the PDN signal is active high and the PUP_signal is inactive high, the NMOS transistor 36 turns ON to couple the DQ_OUT terminal to ground. As long as the slew rate at which the signal at the DQ_OUT terminal transitions to VCCQ and to ground, the buffer 10 shown in FIG. 1 provides adequate performance. However, if maintaining the slew rate constant despite variations in the magnitude of the supply voltage VCCQ is important, the buffer 10 may not provide adequate performance.
The manner in which the slew rate of read data signals from the output buffer 10 varies will now be explained with reference to FIGS. 2A and 2B, which shows the timing of the signals in the output buffer 10 at two different levels of supply voltage. The time delay through the gates are ignored in FIG. 2A and FIG. 2B for simplicity. As illustrated in FIG. 2A, the voltage at the DQ_OUT terminal begins transitioning from low-to-high responsive to the D_PDN_signal transitioning low-to-high at time t0 and the D_PUP signal transition from low-to-high after a short delay tdr at time t1. As further shown in FIG. 2A, the low-to-high transition of the D_PDN_signal causes the PDNEN signal at the output of the inverter 18 (FIG. 1) to transition low, and the low-to-high transition of the D_PUP signal causes the PUPEN_signal at the output of the inverter 16 to also transition low. As a result, the PDNEN signal transitions low before the PUPEN_transitions low with the same delay tdr. The PDNEN signal is coupled through the NAND gate 26 and the inverter 28 to generate a PDN signal, which transitions from high-to-low at time t0. Similarly, The PUPEN_signal is coupled through the NOR gate 22 and the inverter 24 to generate a PUP_signal, which transitions from high-to-low at time t1. The low PDN signal turns OFF the NMOS transistor 36, and the low PUP_signal turns ON the PMOS transistor 32. The delay tdr between the time to at which the NMOS transistor 36 is turned OFF and the time t1 at which the PMOS transistor 32 is turned ON ensures that the NMOS transistor 36 has turned OFF before the PMOS transistor 32 is turned ON.
When the NMOS transistor 36 turns OFF at time t0, the voltage at the DQ_OUT terminal begins increasing even through the PMOS transistor 32 has not yet been turned ON because of the VCCQ/2 bias applied to the DQ_OUT terminal. When the PMOS transistor 32 turns ON at time t1, the transition of the DQ_OUT terminal to a high logic level corresponding to VCCQ continues, and the DQ_OUT terminal reaches the VCCQ voltage at time t2. In reality, DG_OUT may reach VCCQ voltage before of after t2. The rising edge slew rate of the signal at the DQ_OUT terminal is the ratio of the voltage change, i.e., VCCQ, to the transition time, i.e., t2 less t0.
In a similar manner, the voltage at the DQ_OUT terminal begins transitioning from high-to-low at time t3 when the PUP_signal transitions low-to-high responsive to the D_PUP signal transitioning low, thereby turning OFF the PMOS transistor 32.
In a similar manner, the voltage at the DQ_OUT terminal begins transitioning from high-to-low responsive to the D_PUP signal transitioning from high-to-low at time t3 and the D_PDN_signal transitioning high-to-low after a short delay tdf at time t4. The high-to-low transition of the D_PDN_signal causes the PDNEN signal at the output of the inverter 18 (FIG. 1) to transition high, and the high-to-low transition of the D_PUP signal causes the PUPEN_signal at the output of the inverter 16 to also transition high. The PUPEN_signal causes the PUP_signal to transitions from low-to-high at time t3, and the PDNEN signal causes the PDN signal to transition from low-to-high at time t4. The high PUP_signal turns OFF the PMOS transistor 32, and the high PDN signal turns ON the NMOS transistor 36. Again, the delay tdf between the time t3 at which the PMOS transistor 32 is turned OFF and the time t4 at which the NMOS transistor 36 is turned ON ensures that the PMOS transistor 32 has turned OFF before the NMOS transistor 36 is turned ON. When the PMOS transistor 32 turns OFF at time t3, the voltage at the DQ_OUT terminal begins decreasing even through the NMOS transistor 38 has not yet been turned ON because of the VCCQ/2 bias voltage. When the NMOS transistor 38 turns ON at time t4, the transition of the DQ_OUT terminal to a low logic level corresponding to ground continues, and the DQ_OUT terminal reaches zero volts at time t5. The falling edge slew rate of the signal at the DQ_OUT terminal is again the ratio of the voltage change, i.e., VCCQ, to the transition time, i.e., t5 less t3.
The switching characteristics of the output buffer 10 when the magnitude of the power supply voltage VCCQ increases to VCCQ′ is shown in FIG. 2B. The switching times t0-t5 of all signals are labeled in the same manner as in FIG. 2A. The falling edge transition time t2 less t0 and the rising edge transition time t5 less t3 for a supply voltage of VCCQ′ are shown in FIG. 2B as being the same as the falling edge transition time t2 less to and the rising edge transition time t5 less t3 for a supply voltage of VCCQ as shown in FIG. 2A although in practice they may be longer or shorter. In any case, since the transitions between ground the supply voltage is greater when VCCQ′ is larger as shown in FIG. 2B, the slew rates of the signal at the DQ_OUT terminal are also greater. The signal at the output terminal is able to transition between ground the VCCQ′ at this high rate with the greater supply voltage VCCQ′ primarily because the PMOS transistor 32 is turned ON with a greater gate-to-source voltage. The voltage at the DQ_OUT terminal is able to transition low from VCCQ′ to ground at this high rate with the greater supply voltage VCCQ′ primarily because the NMOS transistor 36 is turned ON with a greater gate-to-source voltage because the inverter 28 is normally also powered by the greater supply voltage VCCQ′.
This variation in the slew rate at the DQ_OUT terminal can create problems at high speeds where timing is critical, and it can make it more difficult for memory devices and other integrated circuits containing the output buffer 10 from meeting slew-rate specifications. There is therefore a need for an output buffer that is capable of providing an output signal having rising edge and falling edge slew rates that are substantially insensitive to variations in the magnitude of a voltage supplying power to the output buffer.